This invention relates to a method for manufacturing a semiconductor device having field effect transistors (FET's).
Recently, MOS FET's of which a MOS integrated circuit is comprised are microminiaturized to improve the integration density of the MOS integrated circuit. In this case, in order to make the electrical characteristics of the MOS FET proper, the effective channel length of the MOS FET must be formed to be a predetermined length. It is particularly necessary to prevent the channel length from becoming shorter than a predetermined channel length (hereinafter referred to as "channel-shortening"). In order to prevent such channel-shortening, it is only necessary to shallowly form a diffusion layer which forms a source and drain region near the gate of the MOS FET. If a shallow diffusion layer is formed, however, the resistance of the diffusion layer is increased, providing a bar to a high-speed semiconductor device. One solution to such a problem is disclosed in Japanese Patent Disclosure (KOKAI) No. 54-161282 as proposed by the same inventor as that of this application. This invention is directed to solving the above-mentioned problem from another angle.